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In normal operation according to the truth table above the 7. HC5. 95 shift registers clear pin SCLR should be put on logical high and the 8- bit D- Latch buffer output enable pin G should be put on logical low.

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Sometimes we need to extend or add more IO ports to our microcontroller based project.

Because usually we only have a limited IO port left than the logical choice is to use the serial data transfer method; which usually only requires from one up to four ports for doing the data transfer.

Currently there are few types of modern embedded system serial data transfer interface widely supported by most of the chip s manufactures such as I2.

C read as I square C, SPI Serial Peripheral Interface, 1- Wire One Wire, Controller Area Network CAN, USB Universal Serial Bus and the RS- 2.

RS- 4. 23, RS- 4.

Among these serial data transfer interface types, SPI is considered the fastest synchronous with full duplex serial data transfer interface and can be clocked up to 1.

MHz; that is why it is widely used as the interface method to the high speed demand peripheral such as the Microchip Ethernet controller ENC2.

J6. 0, Multi Media Card MMC Flash Memory, Microchip SPI IO MCP2.

IO ports and to communicate between two microcontrollers with the SPI peripheral where one microcontroller is configured as a master and other as a slave.

The principal we learn here could be applied to other types of microcontroller families.

If more the one SPI devices is connected to the same bus, then we need four ports and use the fourth port SS pin on the ATMega.

If more then three SPI slave devices, then it is better to use from three to eight channels decoder chip such as 7.

HC1. 38 families.

Since the SPI protocol uses full duplex synchronous serial data transfer method, it could transfer the data and at the same time receiving the slave data using its internal shift register.

From the SPI master and slave interconnection diagram above you could see that the SPI peripheral use the shift register to transfer and receive the data, for example the master want to transfer 0b.

By activating the CS chip select pin on the slave device, now the slave is ready to receive the data.

Continuously using the same principal for each bit, the complete data transfer between master and slave will be done in 8 clock cycle.

By using the highest possible clock allowed such as the Microchip MCP2.

S1. 7 SPI slave IO device 1.

As you understand how the SPI principal works, now its time to implement it with the Atmel AVR ATMega.

The following is the list of hardware and software used in this project: 7.

Microchip MCP2. 3S1.

SPI IO Expander. AVRJazz Mega.

AVR ATmega. 16. 8 microcontroller board schema.

Win. AVR for the GNU s C compiler.

Atmel AVR Studio 4 for the coding and debugging environment.

Because the basic operation of SPI peripheral is a shift register, then we could simply use the 8- bit shift register with output latch to expand the output port.

The 1. 6 pins 7. 4HC5.

In normal operation according to the truth table above the 7.

HC5. 95 shift registers clear pin SCLR should be put on logical high and the 8- bit D- Latch buffer output enable pin G should be put on logical low.

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